TestBench연습 2진업다운카운터

■Test Bench : 디자인or모델의 정확성 및 안전성을 확인하는데 사용되는 가상환경.
설계한 디자인(모듈,디자인,회로)의 시뮬레이션을 위해 가상의 입력을 정의

 

▶2진 업다운 카운터

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity up_down_counter is
port ( clock,reset,up_down : in std_logic;
       counter : out std_logic_vector(3 downto 0));
end up_down_counter;
architecture beh of up_down_counter is
signal t_count : std_logic_vector (3 downto 0);
begin
process(clock,reset)
begin
if(reset = '1') then
t_count <= (others => '0');
elsif rising_edge(clock) then
if up_down = '0' then
t_count <= t_count + 1;
else
t_count <= t_count - 1;
end if;
end if;
end process;
counter <= t_count;
end beh;

2진 업다운 카운터 Test Bench

library ieee;
use ieee.std_logic_1164.all;
entity tb_up_down is end tb_up_down;
architecture beh of tb_up_down is
component up_down_counter
port(
 clock: in std_logic;
 reset : in std_logic;
 up_down : in std_logic;
 counter : out std_logic_vector(3 downto 0));
end component;
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal up_down : std_logic := '0';
signal counter : std_logic_vector(3 downto 0);
constant clock_period : time := 20ns;
begin
uut : up_down_counter port map(
clock=>clock,
reset=>reset,
up_down=>up_down,
counter=>counter);
clock_process : process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
stim_proc : process
begin
wait for 20ns;
reset <= '1';
wait for 20ns;
reset <= '0';
up_down <= '0';
wait for 200ns;
up_down <='1';
wait;
end process;
end;